Transistors such as metal oxide semiconductor field effect transistors (MOSFETs) or simply field effect transistors (FETs) or MOS transistors are the core building blocks of the vast majority of semiconductor integrated circuits (ICs). A FET includes source and drain regions between which a current can flow through a channel under the influence of a bias applied to a gate electrode that overlies the channel. Some semiconductor ICs, such as high performance microprocessors and memory arrays, can include millions of FETs. For such ICs, decreasing transistor size and thus increasing transistor density remains a high priority in the semiconductor manufacturing industry. Transistor performance, however, must be maintained even as the transistor size decreases.
Static random access memory (SRAM) integrated circuits (ICs) are widely used, both as stand-alone memories and as embedded memories in, for example, microprocessors. The size of such SRAM ICs has increased markedly so that memories in excess of one million bits are now common. As IC size has increased, so has the processing complexity. The increased IC size requires a reduction in the size of individual components and in the minimum feature size, the minimum width of lines and spaces within an individual component. Processing complexity increases as the feature size decreases because it becomes difficult to precisely define lines and to ensure adequate spacing between features on different processing levels.
Presently known SRAM cells include six transistors and require at least three levels of metal in addition to the gate electrode level. Reliably processing the multiple layers of conductors and the necessary contacts to those conductor levels is difficult, especially when the minimum feature size shrinks to the range of 20 nanometers (nm) or less.
It is also known that high performance field effect transistors (FETs) can be formed in fin-like semiconductor structures, commonly referred to as “FINFETs”. Integrated circuits (ICs), including SRAM cells, are fabricated using such FINFETS. Unlike conventional planar FETs, with FINFETs the semiconductor region containing the source-drain channel has a fin-like shape standing approximately perpendicular to the surface of the substrate die or wafer on which the device is formed. Gate electrodes can be provided on both exposed sides of the fin-like channel region and sometimes along the narrow top edge, although such edge gates are not required. The term “tri-gate” is used to refer to fin-type FETs that have the gate along the narrow top edge as well as along the sides. As used herein, the term “FINFET”, singular or plural, is intended to include all such variations.
A FINFET transistor lends itself to the dual goals of reducing transistor size while maintaining transistor performance. Transistor performance, often measured by its transconductance, is proportional to the width of the transistor channel. In a FINFET the transistor channel is formed at least along the vertical sidewalls of the fin, to facilitate the formation of a wide channel, and thereby increase performance, without significantly increasing the area of the substrate surface required by the transistor.
Even with FINFETs, however, reducing the device size (and, hence, feature size) introduces fabrication problems. Such problems include adverse short channel effects as the gate length shrinks and the attendant variation in threshold voltage (the minimum gate voltage necessary to turn a transistor “ON”) from random dopant fluctuations in the channel. Variations or fluctuations in threshold voltage (Vt), in turn, can lead to mismatched and unmatched transistors. One solution is to fabricate transistors with undoped channels, but fabricating such transistors can be difficult, particularly with devices formed on a bulk semiconductor wafer. Due to the lack of dopant in a fully depleted body, there is little or no random dopant fluctuation driven Vt mismatch, and random telegraph noise (RTN) becomes a limiting matching mechanism for SRAM cells. Process optimization can improve RTN; Vt-mismatch due to RTN is also scaling with area, so that maximizing gate area remains an important objective for future large SRAM arrays.
For low SRAM-cell leakage, gate induced drain leakage (Gidl) is another limiting factor. The increasing doping concentration directly at the gate is needed in order to obtain the drive current for the SRAM devices. This contributes to increasing Gidl.
Accordingly, it is desirable to provide an SRAM integrated circuit having buried FINFETs. In addition, it is desirable to provide methods for fabricating SRAM integrated circuits having buried FINFETS with reduced complexity and increased reliability. Furthermore, other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and the foregoing technical field and background.